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SoC Component Level and Architecture for Wireless systems.
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With the increasing complexity and the additional demand for more programmability, new innovations for improving the energy-efficiency of future wireless systems are needed. In my PhD research I focus on two major approaches: technology-aware architecture design for obtaining high energy-efficient architectures at design-time and dynamic performance-energy scaling for improving the average energy-efficiency at run-time. (1) In emerging deep-sub-micron (DSM) technologies, the influence of wires on energy, performance and area is becoming more and more significant. While negligible in the past, DSM design flows need to incorporate the wire influence early in the design phase. In state-of-the-art design methodologies the real influence becomes only visible at the final place and route stage - by far too late for considering efficient counter-measures. To solve this issue, a semi-custom design flow, which is based on physically characterized building blocks, is proposed. Initial results indicate that more energy-efficient designs can be obtained in shorter time. (2) Systems are conventionally only designed for the worst-case operating mode, i.e., the mode, in which the performance is sufficient to fulfill the most demanding requirements. However, depending on the usage of the system, the maximal performance may not always be required. By trading-off performance vs. energy at run-time, the average energy-efficiency can significantly be increased. We focus mainly on Application Specific Instruction Set Processors (ASIPs), which offer typically a good trade-off between flexibility and efficiency. The concept of run-time scaling was recently demonstrated on a MIMO detector, which is a critical block in a wireless system.
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Project number:
3E090229
Duration of the project:
01.07.2008 - 01.07.2012
Funded research
Nederlands
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