Doctoral research project

Person in charge of the project:
MERTENS ROBERT PIERRE, member of research team Associated Section of ESAT - INSYS, Integrated Systems
Title:
Technology Integration of GaN-on-Si HEMTs for Power Electronics Applications
Project summary:
Group III-N (GaN, AlGaN, and AlN) are very useful material systems to be used at high voltage and under high ambient temperature conditions. This is due to their excellent intrinsic properties, such as wide band gap, large critical electric field and low intrinsic carrier concentration.In addition to material properties, the hetero-structure at AlGaN/GaN interface leads to the formation of 2-DEG (two dimensional electron gas) with high carrier density, high mobility and high saturation velocity which can be utilized to realize an efficient and compact power conversionsystem. Among the substrates (sapphire, SiC, GaN and Si), the epitaxialgrowth and fabrication of these devices on Si substrates are the most cost effective solutions. But in the scope of this PhD, it is sketched out that the parasitic conduction across the III-N/Si interface leads to undesired device breakdown voltage saturation after a certain gate-drain distance. This saturation could be elevated by using thick buffers on Si; however, growing thick buffers are problematic due to the large lattice and thermal mismatch between III-N and Si but additionally it puts an excessive epitaxial growth cost.In this PhD work, novel Si substrate removal approaches to terminate the III/Si interfacial conduction toenhance the breakdown voltage of GaN-DHFETs (double heterostructure field effect transistors) has been studied extensively. Various technological approaches starting from ‘Global Si substrate removal (GSSR)’-to-‘Local Si removal between S-to-D contacts (LRSD)’-to-‘Si trench around draincontact (STAD)’ have been developed. After Si removal, a linear increase in the breakdown voltage with the gate-drain distance is measured compared to a saturated breakdown voltage for the similar devices on Si. A record breakdown voltage of over ~ 2000 V is measured for a gate-drain distance of only 20 µm with a buffer thickness of only 2 µm; however similar breakdown voltage on Si substrate can only be achieved byusing a very thick wafer ~ 7 µm. The main thrust from GSSR-to-LRSD-to-STAD is driven by enhancing device thermal performance. In case of a STAD device (compared to a GSSR or a LRSD device), the thinned Si substrate is still under the gate-region (where the maximum heat is generated) which helps to dissipate the generated heat; confirmed by electrical measurements and thermal simulations. It is presented that after Si removal, devices have un-altered threshold voltages (VTH); confirming no change in 2-DEG channel properties. Other key advantages of Si substrate removal include: (1) high voltage operation under high ambient temperature is possible compared to the devices with Si and (2) the device breakdown voltage is independent of the buffer thickness leading to ~ 2000V breakdown for an optimized sub-micron thin (600 nm) buffer layer. Therefore, optimization of thin buffers followed by Si substrate removal is one of the most attractive solutions towards obtaining low cost,high yield and high manufacturability of GaN power devices fabricated on Si substrates.
ph.D student :
SRIVASTAVA PUNEET
Faculty of Engineering Science
Doctoral Programme in Engineering (Leuven)

ph.D defence : 10.07.2012
Full text ph.D