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Architectural solutions for system-level reliability guarantees
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Reliability is one of the key challenges for technology scaling. Various aspects of reliability affect both wires and CMOS devices as we scale to deep in nanometer space.
Various effects like Time Dependent Dielectric Breakdown (TDDB), Electron Migration (EM) etc affect wires. TDDB and other effects like PBTI and NBTI affect devices. In this thesis we will explore and model these device level reliability problems propagate to the circuit and therefore to the architecture level. On understanding the affects at the architecture level and therefore at the system level, this thesis will also explore innovative solutions to give system level guarantees at a limited cost in terms of area, performance etc. Given that these problems occur during the life-time of the device, this thesis would propose a solution that works over the life-time of the device and the techniques propose adapt over the 'state of the device' during its life-time.
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Project number:
3E110256
Duration of the project:
07.03.2011 - 07.03.2015
Funded research
Nederlands
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